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1 features ? low-voltage and standard-voltage operation ? 1.8 (v cc = 1.8v to 3.6v) ? internally organized as 16,384 x 8 ? two-wire serial interface ? schmitt trigger, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 1 mhz (3.6v, 2.5v), and 400 khz (1.8v) compatibility ? write protect pin for hardware and software data protection ? 64-byte page write mode (par tial page writes allowed) ? self-timed write cycle (5 ms max) ? high reliability ? endurance: one million write cycles ? data retention: 40 years ? lead-free/halogen-free devices available ? 8-lead jedec pdip, 8-lead jede c soic, 8-lead ultra thin mini map, 8-lead ultra thin small array package (sap), 8-le ad tssop, and 8-ball dbga2 tm packages ? die sales: wafer form, waffle pack and bumped wafers description the AT24C128B provides 131,072 bits of se rial electrically erasable and programma- ble read-only memory (eeprom ) organized as 16,384 wo rds of 8 bits each. the device?s cascadable feature allows up to ei ght devices to share a common two-wire bus. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the devices are available in space-saving 8-lead jedec pdip, 8-le ad jedec soic, 8-lead ultra thin mini map, 8-lead ultra thin sap, 8-lead tssop, and 8-ball dbga2 packages. in addition, the entire family is available in a 1.8v (1.8v to 3.6v) version. two-wire serial eeprom 128k (16,384 x 8) AT24C128B preliminary rev. 5208a?seepr?1/07 table 1. pin configurations pin name function a0?a2 address inputs sda serial data scl serial clock input wp write protect nc no connect gnd ground a0 a1 a2 gnd vcc wp scl sda 1 2 3 4 8 7 6 5 vcc wp scl sda 8 7 6 5 1 2 3 4 a0 a1 a2 gnd 8 7 6 5 1 2 3 4 vcc wp scl sda a0 a1 a2 gnd 8- l ea d pdip 8-lead soic 8-lead dbga2 a0 a1 a2 gnd vcc wp scl sda 1 2 3 4 8 7 6 5 8-lead tssop bottom view 8 7 6 5 1 2 3 4 vcc wp scl sda a0 a1 a2 gnd 8-lead ultra thin mini map bottom view 8 7 6 5 1 2 3 4 vcc wp scl sda a0 a1 a2 gnd 8-lead ultra thin sap bottom view
2 AT24C128B [preliminary] 5208a?seepr?1/07 figure 1. block diagram absolute maximum ratings* operating temperature ......................................? 55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +5.0v maximum operating voltage ............................................ 4.3v dc output current........................................................ 5.0 ma
3 AT24C128B [preliminary] 5208a?seepr?1/07 pin description serial clock (scl): the scl input is used to positive-edge clock data into each eeprom device and negat ive-edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open- drain driven and may be wire-ored with any number of other open-drain or open-collector devices. device/page addresses (a2, a1, a0): the a2, a1, and a0 pins are device address inputs that are hardwired (directly to gnd or to vcc) for compatibility with other at24cxx devices. when the pins are hardwired, as ma ny as eight 128k devic es may be addressed on a single bus system. (device addressing is di scussed in detail under ?device addressing,? page 8.) a device is selected when a corresp onding hardware and software match is true. if these pins are left floating, the a2, a1, and a0 pins will be intern ally pulled down to gnd. how- ever, due to capacitive coupling that may appear during customer applications, atmel recommends always connecting the address pins to a known state. when using a pull-up resistor, atmel recommends using 10k ? or less. write protect (wp): the write protect input, when connected to gnd, allows normal write operations. when wp is connected directly to vcc, all write operations to the memory are inhibited. if the pin is left floating, the wp pin will be interna lly pulled down to gnd. however, due to capacitive coupling that may appear during customer applications, atmel recommends always connecting the wp pins to a known stat e. when using a pull-up resistor, atmel recom- mends using 10k ? or less. memory organization AT24C128B, 128k serial eeprom: the 128k is internally organized as 256 pages of 64 bytes each. random word addressing requires a 14-bit data word address.
4 AT24C128B [preliminary] 5208a?seepr?1/07 table 1. pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. table 2. dc characteristics notes: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +1.8v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , scl) 6 pf v in = 0v applicable over recommended operating range from: t ai = ? 40 c to +85 c, v cc = +1.8v to +3.6v (unless otherwise noted) symbol parameter test co ndition min typ max units v cc1 supply voltage 1.8 3.6 v i cc1 supply current v cc = 3.6v read at 400 khz 1.0 2.0 ma i cc2 supply current v cc = 3.6v write at 400 khz 2.0 3.0 ma i sb1 standby current (1.8v option) v cc = 1.8v v in = v cc or v ss 1.0 a v cc = 3.6v 3.0 i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ? 0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
5 AT24C128B [preliminary] 5208a?seepr?1/07 table 3. ac characteristics (industrial temperature) notes: 1. this parameter is ensured by characterization and is not 100% tested. 2. ac measurement conditions: r l (connects to v cc ): 1.3 k ? (2.5v, 3.6v), 10 k ? (1.8v) input pulse voltages: 0.3 v cc to 0.7 v cc input rise and fall times: 50 ns input and output timing reference voltages: 0.5 v cc applicable over recommended operating range from t ai = ? 40 c to +85 c, v cc = +1.8v to +3.6v, cl = 100 pf (unless oth- erwise noted). test conditions are listed in note 2. symbol parameter 1.8-volt 2.5, 3.6-volt units min max min max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.3 0.4 s t high clock pulse width high 0.6 0.4 s t i noise suppression time (1) 100 50 ns t aa clock low to data out valid 0.05 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start (1) 1.3 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start set-up time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in set-up time 100 100 ns t r inputs rise time (1) 0.3 0.3 s t f inputs fall time (1) 300 100 ns t su.sto stop set-up time 0.6 0.25 s t dh data out hold time 50 50 ns t wr write cycle time 5 5 ms endurance (1) 25c, page mode, 3.3v 1,000,000 write cycles
6 AT24C128B [preliminary] 5208a?seepr?1/07 device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 2). data changes during scl high periods will indica te a start or stop cond ition as defined below. figure 2. data validity start condition: a high-to-low transition of sda with scl high is a start condition that must precede any other command (see figure 3). figure 3. start and stop definition stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop comm and will place the eeprom in a standby power mode (see fig- ure 3). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a ?0? during the ninth cl ock cycle to acknowl- edge that it has received each word. standby mode: the AT24C128B features a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations. sda scl start stop
7 AT24C128B [preliminary] 5208a?seepr?1/07 software reset: after an interruption in protocol, po wer loss or system reset, any 2-wire part can be protocol reset by following these step s: (a) create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below. the device is ready for next communication after above steps have been completed. figure 4. bus timing figure 5. write cycle timing note: 1. the write cycle time t wr is the time from a valid stop c ondition of a write sequence to the end of the internal clear/write cycle. scl sda 123 89 start bit start bit stop bit dummy clock cycles t wr (1) stop condition start condition wordn ack 8th bit s cl s da
8 AT24C128B [preliminary] 5208a?seepr?1/07 figure 6. output acknowledge device addressing the 256k eeprom requires an 8- bit device address word followi ng a start condition to enable the chip for a read or write operation (see fi gure 7). the device address word consists of a mandatory ?1?, ?0? sequence for the first four mo st significant bits as shown. this is common to all two-wire eeprom devices. figure 7. device address the next three bits are the a2, a1, a0 device addr ess bits to allow as many as eight devices on the same bus. these bits must compare to their corresponding hardwired input pins. the a2, a1, and a0 pins use an internal proprietary ci rcuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device addr ess is the read/write operation select bit. a read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a ?0?. if a compare is not made, the device will retu rn to a standby state. data security: the AT24C128B has a hardware data protection scheme that allows the user to write protect the whole memory when the wp pin is at v cc . msb 1 0 1 0 a2 a1 a0 r/w lsb
9 AT24C128B [preliminary] 5208a?seepr?1/07 write operations byte write: a write operation requires two 8-bit data word addresses following the device address word and ackn owledgment. upon receipt of this address, the eeprom will again respond with a ?0? and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a ?0?. the addressing device, such as a microcontroller, must then terminate the write sequence with a stop condition. at this time the eeprom enters an internally-timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will no t respond until the write is complete (see figure 8). figure 8. byte write note: * = don?t care bit page write: the 256k eeprom is capable of 64-byte page writes. a page write is initiated the sa me way as a byte write, but th e microcontroller does not send a stop condition after the first da ta word is clocked in. instea d, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. the eeprom will respond with a ?0? af ter each data word received. the microc ontroller must ter- minate the page write sequence with a stop condition (see figure 9). figure 9. page write note: * = don?t care bit the data word address lower six bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, inter nally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 64 data words are transmitted to the eeprom, the data word addres s will ?roll over? and previous data will be overwritten. the address ?roll over? during write is from the last byte of the current page to the first byte of the same page. acknowledge polling: once the internally-timed wr ite cycle has started and the eeprom inputs are disabled, acknowledge polling c an be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if t he internal write cycle has co mpleted will the eeprom respond with a ?0?, allowing the read or write sequence to continue.
10 AT24C128B [preliminary] 5208a?seepr?1/07 read operations read operations are initiated the same way as write operations with th e exception that the read/write select bit in the device address word is set to ?1?. there are three read operations: current address read, random address read, and sequential read. current address read: the internal data word addr ess counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page, to the first byte of the first page. once the device address with the read/write se lect bit set to ?1? is clocked in and acknowl- edged by the eeprom, the curr ent address data word is se rially clocked out. the microcontroller does not respond with an input ?0? but does generate a following stop condition (see figure 10). figure 10. current address read random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address wo rd and data word address are clocked in and acknowledged by the eeprom, the microcontr oller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. th e eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a ?0? but does generate a follow- ing stop condition (see figure 11). figure 11. random read note: * = don?t care bit
11 AT24C128B [preliminary] 5208a?seepr?1/07 sequential read: sequential reads are initiated by either a current address read or a ran- dom address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eepr om receives an ackn owledge, it will cont inue to increment the data word address and serially clock out sequential data words. when the memory address limit is reache d, the data word address will ?roll over? and the sequential read will con- tinue. the sequential read operation is terminated when the microcontroller does not respond with a ?0? but does generate a following stop condition (see figure 12). figure 12. sequential read
12 AT24C128B [preliminary] 5208a?seepr?1/07 notes: 1. ?-b? denotes bulk. 2. ?-t? denotes and tape and reel. soic=4k. tssop, dbga2, minimap, and sap=3k. 3. available in waffle pack, tape and reel, and wafer form; or der as sl788 for inkless wafer form. bumped die available upon request. please contact serial interface marketing. AT24C128B ordering information ordering code voltage package operation range AT24C128B-pu (bulk form only) AT24C128Bn-sh-b (1) (nipdau lead finish) AT24C128Bn-sh-t (2) (nipdau lead finish) AT24C128B-th-b (1) (nipdau lead finish) AT24C128B-th-t (2) (nipdau lead finish) AT24C128By6-yh-t (2) (nipdau lead finish) AT24C128By7-yh-t (2) (nipdau lead finish) AT24C128Bu2-uu-t (2) (nipdau lead finish) 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 8p3 8s1 8s1 8a2 8a2 8y6 8y7 8u2-1 lead-free/halogen-free industrial temperature (? 40 c to 85 c) AT24C128B-w11 (3) 1.8 die sale industrial temperature (? 40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8u2-1 8-ball, die ball grid array package (dbga2) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8y6 8-lead, 2.00 mm x 3.00 mm body, 0.50 mm pitch, ultra thin mini map, dual no l ead package, (dfn), (mlp2x3mm) 8y7 8-lead, 6.00 mm x 4.90 mm body, ultra thin, dual footprint, non-leaded, small array package (sap) options ? 1.8 low-voltage (1.8v to 3.6v)
13 AT24C128B [preliminary] 5208a?seepr?1/07 packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba, for additional information . 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a ? ? 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 ? ? 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view
14 AT24C128B [preliminary] 5208a?seepr?1/07 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
15 AT24C128B [preliminary] 5208a?seepr?1/07 8u2-1 ? dbga2 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. po8u2-1 a 6/24/03 common dimensions (unit of measure = mm) symbol min nom max note 8u2-1, 8-ball, 2.35 x 3.73 mm body, 0.75 mm pitch, small die ball grid array package (dbga2) a 0.81 0.91 1.00 a1 0.15 0.20 0.25 a2 0.40 0.45 0.50 b 0.25 0.30 0.35 1 d 2.35 bsc e 3.73 bsc e 0.75 bsc e1 0.74 ref d 0.75 bsc d1 0.80 ref 1. dimension 'b' is measured at the maximum solder ball diameter. this drawing is for general information only. d a side view top view bottom view 8 solder balls 1 a b c d 2 (e1) e a1 ball pad corner (d1) 1. b a1 a2 d a1 ball pad corner e
16 AT24C128B [preliminary] 5208a?seepr?1/07 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
17 AT24C128B [preliminary] 5208a?seepr?1/07 8y6 ? map 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8y6 , 8-lead 2.0 x 3.0 mm body, 0.50 mm pitch, utlra thin mini-map, dual no lead package (dfn) ,(mlp 2x3) c 8y6 8/26/05 notes: 1. this drawing is for general information only. refer to jedec drawing mo-229, for proper dimensions, tolerances, datums, etc. 2. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. common dimensions (unit of measure = mm) symbol min nom max note d 2.00 bsc e 3.00 bsc d2 1.40 1.50 1.60 e2 - - 1.40 a - - 0.60 a1 0.0 0.02 0.05 a2 - - 0.55 a3 0.20 ref l 0.20 0.30 0.40 e 0.50 bsc b 0.20 0.25 0.30 2 a2 b (8x) pin 1 id pin 1 index area a1 a3 d e a l (8x) e (6x) 1.50 ref. d2 e2
18 AT24C128B [preliminary] 5208a?seepr?1/07 8y7 ? ut sap 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. 8y7 , 8-lead (6.00 x 4.90 mm body) ultra-thin soic array package (utsap) y7 b 8y7 10/13/05 common dimensions (unit of measure = mm) symbol min nom max note a ? ? 0.60 a1 0.00 ? 0.05 d 5.80 6.00 6.20 e 4.70 4.90 5.10 d1 3.30 3.40 3.50 e1 3.90 4.00 4.10 b 0.35 0.40 0.45 e 1.27 typ e1 3.81 ref l 0.50 0.60 0.70 d1 pin 1 id e1 l b e1 e pin 1 index area a e d a1 a
19 AT24C128B [preliminary] 5208a?seepr?1/07 revision history doc. rev. date comments 5208a 1/2007 initial document release.
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